As the number of write/erase (W/E) cycles performed in a flash memory increases, the data retention capability of the flash memory is reduced and the probability of failures is increased. Such failures are usually related to wearing of an oxide isolation layer of cells in the flash memory due to electrons passing through the oxide isolation layer during W/E cycles and generating electron trap sites. Such failures can be manifested in several ways, such as by failing to erase or program a block of cells in the flash memory or by having reduced cell data retention (i.e., a reduced ability to store data reliably for a certain period of time). As cell dimensions shrink, a corresponding reduction in endurance may become a limiting factor affecting commercial viability non-volatile memories, such as NAND-based flash memory.
A data stream with a distribution that is significantly different than a distribution induced by an independent and identically distributed (i.i.d.) bit source having equal probability for 1 and 0 is said to be “shaped.” Examples of shaped data include data that contains a significantly higher number of 1-s than 0-s, or vice versa (e.g., data which contains a significantly higher number of 0-s than 1-s). An amount of shaping may correspond to an entropy of a data source that is determined relative to an alphabet of data and its distribution. For example, binary entropy is the entropy of an i.i.d. data source having an alphabet {0, 1}. Binary entropy can be determined as H(p)=−p(0)log2p(0)−p(1)log2p(1), where p(0) is the probability that the data source will generate the value 0 and p(1) is the probability that the data source will generate the value 1. If the data source has a distribution of 90% 0-s and 10% 1-s, the entropy H(p) is approximately equal to 0.47. As another example, if an i.i.d. data source has an alphabet that contains four symbols {A, B, C, D}, the entropy of the data source can be determined as H(p)=−p(A)log4p(A)−p(B)log4p(B)−p(C)log4p(C)−p(D)log4p(D). If A, B, C, and D are represented in the data by the ordered pairs (0,0), (0,1), (1,0), and (1,1), respectively, low entropy but equal distributions of 1-s and 0-s may result, such as when p(0,0)=p(1,1)=0.05 and p(1,0)=p(0,1)=0.45.
Any data with entropy significantly lower than one (where one is the binary entropy of data having 50% zeros and 50% ones) can be considered to be shaped. Criteria for considering a value of entropy to be significantly lower than ‘1’ may vary according to each particular implementation. Shaped data may have a higher number of 1-s because in conventional NAND flash systems, ‘1’ typically represents an erase state while ‘0’ typically represents a programmed state. Shaping data to have a higher number of 1-s may increase a useful life of a flash memory because increasing the proportion of memory cells that are set to the erase state (i.e., cells set to logical ‘1”) causes less wear of the flash cells and increases the number of W/E cycles that the NAND flash cells may undergo while maintaining a pre-defined storage reliability.
In multi-level cell (MLC) devices in which programming is used in order to store reliable data, any data stored in the MLC cells may be first placed in a single-level cell (SLC) cache. A partition of the flash memory that is most susceptible to wearing may be a SLC partition that includes the SLC cache. The SLC cache may be a binary partition of a flash memory die. Conventionally, each cell in the SLC cache stores only one bit and has only two distinct voltage regions that are separated. In many cases, data can be reliably programmed to the SLC partition in a direct, simple, and speedy manner, while programming the data into the MLC partition is a more complex and slower process. Another useful characteristic of the SLC partition is that it is possible to program the SLC partition in smaller data size chunks. For example, when storing a 16 kilobyte (KB) page, data may be programmed to a SLC cache in chunks of 4 KB, while for MLC programming the smallest data size chunk that can be programmed may be 16 KB.
With increasing use of “random” (i.e., non-sequential) type of programming of memory devices, such as solid state drives, data is typically first programmed to a SLC cache. As a result, in MLC NAND flash devices, a limiting factor of a useful life of a flash based system may be the endurance of the SLC partition.
Data may be first stored temporarily in an SLC partition and later moved to a MLC partition for long term storage. The SLC partition is typically much smaller than the MLC partition. Therefore, the SLC partition may be subject to higher wearing pressure, since most of the data targeted to the MLC partition passes for a short period through the SLC partition (i.e., first stored at the SLC and then copied to the MLC). In many cases, wearing of the SLC partition may be the factor that limits the useful life of a flash memory system. Extending life of the SLC partition may therefore extend the useful life of the flash memory system. Various methods may be used to shape compressible data to form shaped data, such that the portion of 1-s in the shaped data is larger than the portion of 0-s. Because ‘1’ typically corresponds to the Erase state in a SLC partition, the SLC partition may experience less wear when programmed with shaped data.
Decoding shaped data using conventional soft decode techniques that include estimating an initial reliability for each bit (such as a log-likelihood ratio (LLR)) that is independent of the shaping level of the data results in non-optimal decoding and reduced correction capability compared to theoretically achievable correction capability. Another issue is related to a problem that may arise when programming shaped data into a MLC partition. Shaped data stored in a MLC partition may result in unbalanced bit error rates (BER) between different logical pages of the MLC partition, and thus one of the logical pages may incur higher bit error rate. A problem may arise when copying the shaped data from the SLC cache to the MLC partition causing an increase in the MLC error rate of one or more of the MLC logical pages due to unbalanced bit error rates (BER) between different logical pages of the MLC WordLine (WL). Thus, shaping methods that may help solve the problem of the wear of the SLC cache at the same time may increase the error rate of the data stored in MLC. It is desired to have a shaping mechanism which enhances the SLC endurance on one hand, while on the other hand does not increase the MLC error rate. Moreover, it is desired to have mechanism that improves the correction capability for the MLC data.
Increased error rate due to unbalanced block error rates resulting from storing shaped data may be at least partially compensated by the use of additional soft bits during decoding of data read from a MLC partition, that can boost the decoder's correction capability. However, reading additional soft bits impacts read throughput performance and power consumption. Reading additional soft bits from a flash memory includes sensing the flash memory with additional read threshold voltages. A total number of sensing operations to read the soft bits may be a factor of 3 to 7 higher than a number of sensing operations for reading the hard bits only, resulting in increased power consumption and lower throughput.